ADELIA Luna Analog deep learning inference accelerator in 22 nm

ADELIA Luna 01 is a highly efficient, low-latency accelerator designed to run lightweight neural networks (NNs) and perform inference on data streamed over the SPI bus. NN models can be exported in ONNX format and deployed on ADELIA. A dedicated tool for seamless deployment of AI models supports quantization, relearning and mapping of NNs for ADELIA. Communication takes place entirely via SPI. After a power-on reset, the NN configuration is written to the SRAM configuration and weight memory. ADELIA continuously performs inferences and the results can be retrieved via SPI when the Inference Ready output pin provides a positive voltage edge as an interrupt signal. The results can be processed by an external microcontroller to initiate higher level protocols. This capability makes ADELIA suitable for implementing event-based protocols in various applications. The ADELIA family is scalable and offers the ability to provide additional cores in a customized design with minimal development time and cost.