embedded award 2023: SoC/IC/IP design nominees

Energy harvesting wireless SoCs, the industry’s most scalable RISC-V IP core and an extremely energy-efficient SoC

Atmosic ATM Series Energy Harvesting Wireless SoCs

Exhibitor: Atmosic
Hall/Booth: 4A/4A-639

Did you know 3 Billion batteries are thrown away every year in landfills? That's nearly 100 batteries.... per second! The situation will not get any better given we are on course to create 27 Billion Connected IoT devices by 2025.

So IoT needs to think differently, our series of SoCs are designed to use such low power and offer standards-based wireless communication (such as Bluetooth), using only a single battery for the lifetime of the product, or leveraging integrated energy harvesting capabilities from RF, photovoltaic, thermal or motion sources.

This is good for the user given their product have little to no battery maintenance, and its good for the environment as the number of batteries ending in landfill can be substantially reduced
Power reduction techniques typically found only in digital are extended to analogue and mixed-signal circuits. Sensor, data and energy management all can be achieved while the MCU is asleep.

Energy sources are used in priority ... Energy harvested sources 1st, storage 2nd and batteries last. Integrated energy management removes the need for multiple inefficient conversions All SoCs use standards-based wireless (eg. Bluetooth) ensuring more IoT projects can leverage the capability

MIPS eVocore P8700 multiprocessor system

Exhibitor: MIPS (RISC-V)
Hall/Booth: 4A/4A-620

Across markets such as autonomous driving, Advanced Driver Assistance Systems (ADAS), datacenter, high performance computing, 5G communications and others, increasingly variable workloads are driving the need for heterogeneous computing. In this environment, system designers need CPUs that are highly scalable, enabling them to configure their systems to use the right processor for each specific workload.

Heterogeneous systems are all about flexibility, so CPUs must be designed with this in mind. If you can make the CPUs extremely scalable to achieve high throughput through multi-threading and high performance through multiple cores and clusters, all with shared memory between all cores, main memory, and I/O devices, this solves a huge challenge for designers.

In addition, with the rise of RISC-V popularity, there is a wide range of RISC-V CPUs available, but it’s not enough to build a well-performing CPU. Customers today need solutions that will help them get to market quickly with proven, differentiated systems. Key enablers are silicon-proven processors, security, and optimizations for specific applications such as support for automotive functional safety.

The MIPS eVocore P8700 multiprocessing system brings a new level of performance to RISC-V. It is the industry’s highest performance, most scalable RISC-V IP core – the first with Out-of-Order (OoO) processing and coherent multi-threaded, multi-core and multi-cluster scalability.

With the P8700, designers can uniquely combine clusters of multi-threaded, multi-core CPUs – eVocore processors and other accelerators – in unique configurations to achieve the right balance of performance and power consumption.

A Coherence Manager maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. The P8700 has single-threaded performance greater than other current RISC-V CPU IP offerings. A P8700 with one thread delivers 15% more performance than the leading competitor. The scalability of the P8700, able to scale up to 64 clusters, 512 cores and 1,024 harts/threads, takes this to another level: the P8700 delivers 70% more performance when using two threads.

Multi-threading provides other unique benefits through a mechanism that enables switching to high-priority tasks with zero latency. Together with hardware virtualization capability in the cores, this enables better utilization of system resources. Foundational technologies for specific markets are also key differentiators. This includes proven robust safety capabilities for ISO 26262 ASIL-B(D) and ASIL-D systems. The P8700 is also the first CPU in silicon with support for automotive-grade Linux.