embedded award 2024: Safety & security nominees

Security improvements by adding protection against memory errors to the design, a security framework for an IoT device and a comprehensive solution for diagnostic and security needs 

Codasip CHERI Technology 

Exhibitor: Codasip 
Hall/Booth: 4/4-368 

Security vulnerabilities often hit the headlines. It’s been the case for some time now and does not seem to stop. The consequences for product makers, industries, governments, and end customers, are real. There is security and privacy of course – but also the cost of these data breaches. Each year, Microsoft lists CVEs (Common Vulnerabilities and Exposures) after analyzing cyberattacks. It appears that ~70% of the vulnerabilities they reported are caused by memory safety issues.

At Codasip we are convinced that the way CHERI technology revisits fundamental design choices in hardware and software will prevent this problem, and significantly improve system security. By adding protection against memory errors to the design, we are increasing the robustness of our IP to prevent cyberattacks resulting from memory misuse and unexpected software defects.

CHERI also improves safety by limiting the impact of memory errors within contained areas of code. Because CHERI technology can be applied selectively to critical functions, it is possible to enhance the security of existing products with a small effort, often through a simple code recompilation. The huge pool of existing C/C++ software can therefore still be leveraged in more secure systems. 

We are making Capability Hardware Enhanced RISC Instructions (CHERI) available in our RISC-V processor cores. CHERI extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization. The technology has been developed by the University of Cambridge during the last decade and is now for the first time available in a commercially licensable product.

We are able to implement the CHERI technology thanks to Codasip Studio. This is our unique collection of tools for fast and easy designing or modification of processors. Using Codasip Studio, we have added built-in, fine-grained memory protection by extending the RISC-V ISA with CHERI-based custom instructions. To enable the use of these instructions, we are also delivering the software environment to take advantage of CHERI technology, bringing a full software development flow to add memory protection.

Key capabilities of Codasip Studio include rapid architecture exploration, automated generation of a custom compiler that understands custom hardware and how to take advantage of it, and automated generation of power and area-optimized synthesizable, human-readable RTL. 

STM32Trust TEE Secure Manager 

Exhibitor: STMicroelectronics 
Hall/Booth: 4A/4A-148

Developing a security framework for an IoT device, is difficult. When it also requires benefitting from Arm(R) TrustZone(R) isolation capabilities, the complexity get inaccessible for most of developers & manufacturers. Complexity starts from defining the threat models, configuring the multiple hardware IP, memories, DMAs & peripherals, coding the framework, securing the production sites for provisioning of the code and purchasing and installing safely the required digital identities, and all of this with sufficient hardening against multiple potential attacks.

Very often end customers want a security assurance, forcing the developer to engage into complex certification procedures. Do IoT manufacturers have the technical competencies and willingness to reach such a hard goal? Moreover, do they have the mean to maintain it over time and products? 

Innovation of our STM32Trust TEE Secure Manager relies on: 

• An Arm PSA API compliant turnkey security framework
• With all security services covering most common need for IoT devices
• Hardened to reach PSA & SESIP level 3 certifications (available on TrustCB & Arm PSA websites since January 2024)
• In-ST-factory provisioned digital identities to connects seamlessly to clouds and servers, removing need for complex secret provisioning flows
• Developpement kits removing totally the need for complex configuration of security IP, peripherals and memories
• Exhaustive toolset for configuration, firmware and key provisioning within untrusted manufacturing infrastructures
• A guarantee for Long Term Support (LTS), including bug fixing and security updates
• The support from ST recognized team of experts, with add-on qualified partner for premium support and services
• Cherry on the cake: a level3 isolation allowing software partner IP protection, protecting IP confidentiality from development to in-the-field runtime execution At the end of these points are reducing time to market, hence costs, improving both competitiveness and reliance of the device manufactures within an extremely competitive landscape.  

Exein Runtime

Exhibitor: Exein 
Hall/Booth: 5/5-170 

Exein Runtime for ESP32 addresses critical challenges in the development and maintenance of IoT devices, providing a comprehensive solution for diagnostic and security needs. One primary problem it solves is the difficulty in monitoring and troubleshooting device issues during development or in specific environments. Developers often face challenges like network disconnections, unexpected crashes, continuous reboots, and unreachable devices.

Exein Runtime offers a convenient dashboard that empowers users to investigate and identify the root causes of these issues efficiently. The product delivers valuable insights into the health and security metrics of ESP32 devices through its dashboard. Users can monitor essential information such as reset reasons, task metrics, coredump files, network metrics, kernel configuration, system metrics, and various hardware-related details. This holistic approach to monitoring allows for a comprehensive understanding of the device's behavior, facilitating quick and effective issue resolution.

The integration of a Machine Learning (ML) model using TensorFlowLite adds a proactive dimension to the solution. The model calculates an anomaly score based on the time series of executed tasks, enabling the detection of abnormal behavior. This capability is crucial for identifying potential security threats or abnormal device operation. Moreover, the ML model supports remote data collection, contributing to ongoing model training and enhancement. 

The innovation of Exein Runtime for ESP32 lies prominently in its integration of Machine Learning (ML) to enhance diagnostic and security capabilities for IoT devices. This ML component introduces a proactive approach to issue detection and resolution. The core innovation is the ML model's ability to calculate an anomaly score based on the time series of executed tasks. This feature empowers the system to recognize abnormal behavior, enabling early detection of potential security threats or operational irregularities.

The ML model becomes a crucial element in the device's overall health monitoring, surpassing traditional reactive methods and enabling preemptive actions. Remote data collection, facilitated through Protobuf, adds another layer of innovation. This feature allows the ML model to continuously learn and adapt by gathering data from the device and incorporating it into ongoing model training. This iterative learning process ensures that the ML model evolves and remains effective in identifying new patterns or anomalies over time.